Xemu [doxygen]  hyppo 0a42be3a057156924bc1b626a687bd6e27349c45 @ Sat 19 Mar 02:15:11 CET 2022
opl3.c
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1 /* Nuked OPL3
2  * Copyright (C) 2013-2020 Nuke.YKT
3  *
4  * This file is part of Nuked OPL3.
5  *
6  * Nuked OPL3 is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU Lesser General Public License as
8  * published by the Free Software Foundation, either version 2.1
9  * of the License, or (at your option) any later version.
10  *
11  * Nuked OPL3 is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public License
17  * along with Nuked OPL3. If not, see <https://www.gnu.org/licenses/>.
18 
19  * Nuked OPL3 emulator.
20  * Thanks:
21  * MAME Development Team(Jarek Burczynski, Tatsuyuki Satoh):
22  * Feedback and Rhythm part calculation information.
23  * forums.submarine.org.uk(carbon14, opl3):
24  * Tremolo and phase generator calculation information.
25  * OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
26  * OPL2 ROMs.
27  * siliconpr0n.org(John McMaster, digshadow):
28  * YMF262 and VRC VII decaps and die shots.
29  *
30  * version: 1.8
31  */
32 
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include "xemu/opl3.h"
37 
38 #define RSM_FRAC 10
39 
40 // Channel types
41 
42 enum {
43  ch_2op = 0,
44  ch_4op = 1,
45  ch_4op2 = 2,
46  ch_drum = 3
47 };
48 
49 // Envelope key types
50 
51 enum {
52  egk_norm = 0x01,
53  egk_drum = 0x02
54 };
55 
56 
57 //
58 // logsin table
59 //
60 
61 static const uint16_t logsinrom[256] = {
62  0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471,
63  0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365,
64  0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd,
65  0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261,
66  0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f,
67  0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd,
68  0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195,
69  0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166,
70  0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c,
71  0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118,
72  0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8,
73  0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db,
74  0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1,
75  0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9,
76  0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094,
77  0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081,
78  0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070,
79  0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060,
80  0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052,
81  0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045,
82  0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039,
83  0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f,
84  0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026,
85  0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e,
86  0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017,
87  0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011,
88  0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c,
89  0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007,
90  0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004,
91  0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002,
92  0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001,
93  0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000
94 };
95 
96 //
97 // exp table
98 //
99 
100 static const uint16_t exprom[256] = {
101  0x7fa, 0x7f5, 0x7ef, 0x7ea, 0x7e4, 0x7df, 0x7da, 0x7d4,
102  0x7cf, 0x7c9, 0x7c4, 0x7bf, 0x7b9, 0x7b4, 0x7ae, 0x7a9,
103  0x7a4, 0x79f, 0x799, 0x794, 0x78f, 0x78a, 0x784, 0x77f,
104  0x77a, 0x775, 0x770, 0x76a, 0x765, 0x760, 0x75b, 0x756,
105  0x751, 0x74c, 0x747, 0x742, 0x73d, 0x738, 0x733, 0x72e,
106  0x729, 0x724, 0x71f, 0x71a, 0x715, 0x710, 0x70b, 0x706,
107  0x702, 0x6fd, 0x6f8, 0x6f3, 0x6ee, 0x6e9, 0x6e5, 0x6e0,
108  0x6db, 0x6d6, 0x6d2, 0x6cd, 0x6c8, 0x6c4, 0x6bf, 0x6ba,
109  0x6b5, 0x6b1, 0x6ac, 0x6a8, 0x6a3, 0x69e, 0x69a, 0x695,
110  0x691, 0x68c, 0x688, 0x683, 0x67f, 0x67a, 0x676, 0x671,
111  0x66d, 0x668, 0x664, 0x65f, 0x65b, 0x657, 0x652, 0x64e,
112  0x649, 0x645, 0x641, 0x63c, 0x638, 0x634, 0x630, 0x62b,
113  0x627, 0x623, 0x61e, 0x61a, 0x616, 0x612, 0x60e, 0x609,
114  0x605, 0x601, 0x5fd, 0x5f9, 0x5f5, 0x5f0, 0x5ec, 0x5e8,
115  0x5e4, 0x5e0, 0x5dc, 0x5d8, 0x5d4, 0x5d0, 0x5cc, 0x5c8,
116  0x5c4, 0x5c0, 0x5bc, 0x5b8, 0x5b4, 0x5b0, 0x5ac, 0x5a8,
117  0x5a4, 0x5a0, 0x59c, 0x599, 0x595, 0x591, 0x58d, 0x589,
118  0x585, 0x581, 0x57e, 0x57a, 0x576, 0x572, 0x56f, 0x56b,
119  0x567, 0x563, 0x560, 0x55c, 0x558, 0x554, 0x551, 0x54d,
120  0x549, 0x546, 0x542, 0x53e, 0x53b, 0x537, 0x534, 0x530,
121  0x52c, 0x529, 0x525, 0x522, 0x51e, 0x51b, 0x517, 0x514,
122  0x510, 0x50c, 0x509, 0x506, 0x502, 0x4ff, 0x4fb, 0x4f8,
123  0x4f4, 0x4f1, 0x4ed, 0x4ea, 0x4e7, 0x4e3, 0x4e0, 0x4dc,
124  0x4d9, 0x4d6, 0x4d2, 0x4cf, 0x4cc, 0x4c8, 0x4c5, 0x4c2,
125  0x4be, 0x4bb, 0x4b8, 0x4b5, 0x4b1, 0x4ae, 0x4ab, 0x4a8,
126  0x4a4, 0x4a1, 0x49e, 0x49b, 0x498, 0x494, 0x491, 0x48e,
127  0x48b, 0x488, 0x485, 0x482, 0x47e, 0x47b, 0x478, 0x475,
128  0x472, 0x46f, 0x46c, 0x469, 0x466, 0x463, 0x460, 0x45d,
129  0x45a, 0x457, 0x454, 0x451, 0x44e, 0x44b, 0x448, 0x445,
130  0x442, 0x43f, 0x43c, 0x439, 0x436, 0x433, 0x430, 0x42d,
131  0x42a, 0x428, 0x425, 0x422, 0x41f, 0x41c, 0x419, 0x416,
132  0x414, 0x411, 0x40e, 0x40b, 0x408, 0x406, 0x403, 0x400
133 };
134 
135 //
136 // freq mult table multiplied by 2
137 //
138 // 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10, 12, 12, 15, 15
139 //
140 
141 static const uint8_t mt[16] = {
142  1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 20, 24, 24, 30, 30
143 };
144 
145 //
146 // ksl table
147 //
148 
149 static const uint8_t kslrom[16] = {
150  0, 32, 40, 45, 48, 51, 53, 55, 56, 58, 59, 60, 61, 62, 63, 64
151 };
152 
153 static const uint8_t kslshift[4] = {
154  8, 1, 2, 0
155 };
156 
157 //
158 // envelope generator constants
159 //
160 
161 static const uint8_t eg_incstep[4][4] = {
162  { 0, 0, 0, 0 },
163  { 1, 0, 0, 0 },
164  { 1, 0, 1, 0 },
165  { 1, 1, 1, 0 }
166 };
167 
168 //
169 // address decoding
170 //
171 
172 static const int8_t ad_slot[0x20] = {
173  0, 1, 2, 3, 4, 5, -1, -1, 6, 7, 8, 9, 10, 11, -1, -1,
174  12, 13, 14, 15, 16, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
175 };
176 
177 static const uint8_t ch_slot[18] = {
178  0, 1, 2, 6, 7, 8, 12, 13, 14, 18, 19, 20, 24, 25, 26, 30, 31, 32
179 };
180 
181 //
182 // Envelope generator
183 //
184 
185 typedef int16_t(*envelope_sinfunc)(uint16_t phase, uint16_t envelope);
186 typedef void(*envelope_genfunc)(opl3_slot *slott);
187 
188 static int16_t OPL3_EnvelopeCalcExp(uint32_t level)
189 {
190  if (level > 0x1fff)
191  {
192  level = 0x1fff;
193  }
194  return (exprom[level & 0xff] << 1) >> (level >> 8);
195 }
196 
197 static int16_t OPL3_EnvelopeCalcSin0(uint16_t phase, uint16_t envelope)
198 {
199  uint16_t out = 0;
200  uint16_t neg = 0;
201  phase &= 0x3ff;
202  if (phase & 0x200)
203  {
204  neg = 0xffff;
205  }
206  if (phase & 0x100)
207  {
208  out = logsinrom[(phase & 0xff) ^ 0xff];
209  }
210  else
211  {
212  out = logsinrom[phase & 0xff];
213  }
214  return OPL3_EnvelopeCalcExp(out + (envelope << 3)) ^ neg;
215 }
216 
217 static int16_t OPL3_EnvelopeCalcSin1(uint16_t phase, uint16_t envelope)
218 {
219  uint16_t out = 0;
220  phase &= 0x3ff;
221  if (phase & 0x200)
222  {
223  out = 0x1000;
224  }
225  else if (phase & 0x100)
226  {
227  out = logsinrom[(phase & 0xff) ^ 0xff];
228  }
229  else
230  {
231  out = logsinrom[phase & 0xff];
232  }
233  return OPL3_EnvelopeCalcExp(out + (envelope << 3));
234 }
235 
236 static int16_t OPL3_EnvelopeCalcSin2(uint16_t phase, uint16_t envelope)
237 {
238  uint16_t out = 0;
239  phase &= 0x3ff;
240  if (phase & 0x100)
241  {
242  out = logsinrom[(phase & 0xff) ^ 0xff];
243  }
244  else
245  {
246  out = logsinrom[phase & 0xff];
247  }
248  return OPL3_EnvelopeCalcExp(out + (envelope << 3));
249 }
250 
251 static int16_t OPL3_EnvelopeCalcSin3(uint16_t phase, uint16_t envelope)
252 {
253  uint16_t out = 0;
254  phase &= 0x3ff;
255  if (phase & 0x100)
256  {
257  out = 0x1000;
258  }
259  else
260  {
261  out = logsinrom[phase & 0xff];
262  }
263  return OPL3_EnvelopeCalcExp(out + (envelope << 3));
264 }
265 
266 static int16_t OPL3_EnvelopeCalcSin4(uint16_t phase, uint16_t envelope)
267 {
268  uint16_t out = 0;
269  uint16_t neg = 0;
270  phase &= 0x3ff;
271  if ((phase & 0x300) == 0x100)
272  {
273  neg = 0xffff;
274  }
275  if (phase & 0x200)
276  {
277  out = 0x1000;
278  }
279  else if (phase & 0x80)
280  {
281  out = logsinrom[((phase ^ 0xff) << 1) & 0xff];
282  }
283  else
284  {
285  out = logsinrom[(phase << 1) & 0xff];
286  }
287  return OPL3_EnvelopeCalcExp(out + (envelope << 3)) ^ neg;
288 }
289 
290 static int16_t OPL3_EnvelopeCalcSin5(uint16_t phase, uint16_t envelope)
291 {
292  uint16_t out = 0;
293  phase &= 0x3ff;
294  if (phase & 0x200)
295  {
296  out = 0x1000;
297  }
298  else if (phase & 0x80)
299  {
300  out = logsinrom[((phase ^ 0xff) << 1) & 0xff];
301  }
302  else
303  {
304  out = logsinrom[(phase << 1) & 0xff];
305  }
306  return OPL3_EnvelopeCalcExp(out + (envelope << 3));
307 }
308 
309 static int16_t OPL3_EnvelopeCalcSin6(uint16_t phase, uint16_t envelope)
310 {
311  uint16_t neg = 0;
312  phase &= 0x3ff;
313  if (phase & 0x200)
314  {
315  neg = 0xffff;
316  }
317  return OPL3_EnvelopeCalcExp(envelope << 3) ^ neg;
318 }
319 
320 static int16_t OPL3_EnvelopeCalcSin7(uint16_t phase, uint16_t envelope)
321 {
322  uint16_t out = 0;
323  uint16_t neg = 0;
324  phase &= 0x3ff;
325  if (phase & 0x200)
326  {
327  neg = 0xffff;
328  phase = (phase & 0x1ff) ^ 0x1ff;
329  }
330  out = phase << 3;
331  return OPL3_EnvelopeCalcExp(out + (envelope << 3)) ^ neg;
332 }
333 
334 static const envelope_sinfunc envelope_sin[8] = {
335  OPL3_EnvelopeCalcSin0,
336  OPL3_EnvelopeCalcSin1,
337  OPL3_EnvelopeCalcSin2,
338  OPL3_EnvelopeCalcSin3,
339  OPL3_EnvelopeCalcSin4,
340  OPL3_EnvelopeCalcSin5,
341  OPL3_EnvelopeCalcSin6,
342  OPL3_EnvelopeCalcSin7
343 };
344 
346 {
351 };
352 
353 static void OPL3_EnvelopeUpdateKSL(opl3_slot *slot)
354 {
355  int16_t ksl = (kslrom[slot->channel->f_num >> 6] << 2)
356  - ((0x08 - slot->channel->block) << 5);
357  if (ksl < 0)
358  {
359  ksl = 0;
360  }
361  slot->eg_ksl = (uint8_t)ksl;
362 }
363 
364 static void OPL3_EnvelopeCalc(opl3_slot *slot)
365 {
366  uint8_t nonzero;
367  uint8_t rate;
368  uint8_t rate_hi;
369  uint8_t rate_lo;
370  uint8_t reg_rate = 0;
371  uint8_t ks;
372  uint8_t eg_shift, shift;
373  uint16_t eg_rout;
374  int16_t eg_inc;
375  uint8_t eg_off;
376  uint8_t reset = 0;
377  slot->eg_out = slot->eg_rout + (slot->reg_tl << 2)
378  + (slot->eg_ksl >> kslshift[slot->reg_ksl]) + *slot->trem;
379  if (slot->key && slot->eg_gen == envelope_gen_num_release)
380  {
381  reset = 1;
382  reg_rate = slot->reg_ar;
383  }
384  else
385  {
386  switch (slot->eg_gen)
387  {
389  reg_rate = slot->reg_ar;
390  break;
392  reg_rate = slot->reg_dr;
393  break;
395  if (!slot->reg_type)
396  {
397  reg_rate = slot->reg_rr;
398  }
399  break;
401  reg_rate = slot->reg_rr;
402  break;
403  }
404  }
405  slot->pg_reset = reset;
406  ks = slot->channel->ksv >> ((slot->reg_ksr ^ 1) << 1);
407  nonzero = (reg_rate != 0);
408  rate = ks + (reg_rate << 2);
409  rate_hi = rate >> 2;
410  rate_lo = rate & 0x03;
411  if (rate_hi & 0x10)
412  {
413  rate_hi = 0x0f;
414  }
415  eg_shift = rate_hi + slot->chip->eg_add;
416  shift = 0;
417  if (nonzero)
418  {
419  if (rate_hi < 12)
420  {
421  if (slot->chip->eg_state)
422  {
423  switch (eg_shift)
424  {
425  case 12:
426  shift = 1;
427  break;
428  case 13:
429  shift = (rate_lo >> 1) & 0x01;
430  break;
431  case 14:
432  shift = rate_lo & 0x01;
433  break;
434  default:
435  break;
436  }
437  }
438  }
439  else
440  {
441  shift = (rate_hi & 0x03) + eg_incstep[rate_lo][slot->chip->timer & 0x03];
442  if (shift & 0x04)
443  {
444  shift = 0x03;
445  }
446  if (!shift)
447  {
448  shift = slot->chip->eg_state;
449  }
450  }
451  }
452  eg_rout = slot->eg_rout;
453  eg_inc = 0;
454  eg_off = 0;
455  // Instant attack
456  if (reset && rate_hi == 0x0f)
457  {
458  eg_rout = 0x00;
459  }
460  // Envelope off
461  if ((slot->eg_rout & 0x1f8) == 0x1f8)
462  {
463  eg_off = 1;
464  }
465  if (slot->eg_gen != envelope_gen_num_attack && !reset && eg_off)
466  {
467  eg_rout = 0x1ff;
468  }
469  switch (slot->eg_gen)
470  {
472  if (!slot->eg_rout)
473  {
475  }
476  else if (slot->key && shift > 0 && rate_hi != 0x0f)
477  {
478  eg_inc = ~slot->eg_rout >> (4 - shift);
479  }
480  break;
482  if ((slot->eg_rout >> 4) == slot->reg_sl)
483  {
485  }
486  else if (!eg_off && !reset && shift > 0)
487  {
488  eg_inc = 1 << (shift - 1);
489  }
490  break;
493  if (!eg_off && !reset && shift > 0)
494  {
495  eg_inc = 1 << (shift - 1);
496  }
497  break;
498  }
499  slot->eg_rout = (eg_rout + eg_inc) & 0x1ff;
500  // Key off
501  if (reset)
502  {
504  }
505  if (!slot->key)
506  {
508  }
509 }
510 
511 static void OPL3_EnvelopeKeyOn(opl3_slot *slot, uint8_t type)
512 {
513  slot->key |= type;
514 }
515 
516 static void OPL3_EnvelopeKeyOff(opl3_slot *slot, uint8_t type)
517 {
518  slot->key &= ~type;
519 }
520 
521 //
522 // Phase Generator
523 //
524 
525 static void OPL3_PhaseGenerate(opl3_slot *slot)
526 {
527  opl3_chip *chip;
528  uint16_t f_num;
529  uint32_t basefreq;
530  uint8_t rm_xor, n_bit;
531  uint32_t noise;
532  uint16_t phase;
533 
534  chip = slot->chip;
535  f_num = slot->channel->f_num;
536  if (slot->reg_vib)
537  {
538  int8_t range;
539  uint8_t vibpos;
540 
541  range = (f_num >> 7) & 7;
542  vibpos = slot->chip->vibpos;
543 
544  if (!(vibpos & 3))
545  {
546  range = 0;
547  }
548  else if (vibpos & 1)
549  {
550  range >>= 1;
551  }
552  range >>= slot->chip->vibshift;
553 
554  if (vibpos & 4)
555  {
556  range = -range;
557  }
558  f_num += range;
559  }
560  basefreq = (f_num << slot->channel->block) >> 1;
561  phase = (uint16_t)(slot->pg_phase >> 9);
562  if (slot->pg_reset)
563  {
564  slot->pg_phase = 0;
565  }
566  slot->pg_phase += (basefreq * mt[slot->reg_mult]) >> 1;
567  // Rhythm mode
568  noise = chip->noise;
569  slot->pg_phase_out = phase;
570  if (slot->slot_num == 13) // hh
571  {
572  chip->rm_hh_bit2 = (phase >> 2) & 1;
573  chip->rm_hh_bit3 = (phase >> 3) & 1;
574  chip->rm_hh_bit7 = (phase >> 7) & 1;
575  chip->rm_hh_bit8 = (phase >> 8) & 1;
576  }
577  if (slot->slot_num == 17 && (chip->rhy & 0x20)) // tc
578  {
579  chip->rm_tc_bit3 = (phase >> 3) & 1;
580  chip->rm_tc_bit5 = (phase >> 5) & 1;
581  }
582  if (chip->rhy & 0x20)
583  {
584  rm_xor = (chip->rm_hh_bit2 ^ chip->rm_hh_bit7)
585  | (chip->rm_hh_bit3 ^ chip->rm_tc_bit5)
586  | (chip->rm_tc_bit3 ^ chip->rm_tc_bit5);
587  switch (slot->slot_num)
588  {
589  case 13: // hh
590  slot->pg_phase_out = rm_xor << 9;
591  if (rm_xor ^ (noise & 1))
592  {
593  slot->pg_phase_out |= 0xd0;
594  }
595  else
596  {
597  slot->pg_phase_out |= 0x34;
598  }
599  break;
600  case 16: // sd
601  slot->pg_phase_out = (chip->rm_hh_bit8 << 9)
602  | ((chip->rm_hh_bit8 ^ (noise & 1)) << 8);
603  break;
604  case 17: // tc
605  slot->pg_phase_out = (rm_xor << 9) | 0x80;
606  break;
607  default:
608  break;
609  }
610  }
611  n_bit = ((noise >> 14) ^ noise) & 0x01;
612  chip->noise = (noise >> 1) | (n_bit << 22);
613 }
614 
615 //
616 // Slot
617 //
618 
619 static void OPL3_SlotWrite20(opl3_slot *slot, uint8_t data)
620 {
621  if ((data >> 7) & 0x01)
622  {
623  slot->trem = &slot->chip->tremolo;
624  }
625  else
626  {
627  slot->trem = (uint8_t*)&slot->chip->zeromod;
628  }
629  slot->reg_vib = (data >> 6) & 0x01;
630  slot->reg_type = (data >> 5) & 0x01;
631  slot->reg_ksr = (data >> 4) & 0x01;
632  slot->reg_mult = data & 0x0f;
633 }
634 
635 static void OPL3_SlotWrite40(opl3_slot *slot, uint8_t data)
636 {
637  slot->reg_ksl = (data >> 6) & 0x03;
638  slot->reg_tl = data & 0x3f;
639  OPL3_EnvelopeUpdateKSL(slot);
640 }
641 
642 static void OPL3_SlotWrite60(opl3_slot *slot, uint8_t data)
643 {
644  slot->reg_ar = (data >> 4) & 0x0f;
645  slot->reg_dr = data & 0x0f;
646 }
647 
648 static void OPL3_SlotWrite80(opl3_slot *slot, uint8_t data)
649 {
650  slot->reg_sl = (data >> 4) & 0x0f;
651  if (slot->reg_sl == 0x0f)
652  {
653  slot->reg_sl = 0x1f;
654  }
655  slot->reg_rr = data & 0x0f;
656 }
657 
658 static void OPL3_SlotWriteE0(opl3_slot *slot, uint8_t data)
659 {
660  slot->reg_wf = data & 0x07;
661  if (slot->chip->newm == 0x00)
662  {
663  slot->reg_wf &= 0x03;
664  }
665 }
666 
667 static void OPL3_SlotGenerate(opl3_slot *slot)
668 {
669  slot->out = envelope_sin[slot->reg_wf](slot->pg_phase_out + *slot->mod, slot->eg_out);
670 }
671 
672 static void OPL3_SlotCalcFB(opl3_slot *slot)
673 {
674  if (slot->channel->fb != 0x00)
675  {
676  slot->fbmod = (slot->prout + slot->out) >> (0x09 - slot->channel->fb);
677  }
678  else
679  {
680  slot->fbmod = 0;
681  }
682  slot->prout = slot->out;
683 }
684 
685 //
686 // Channel
687 //
688 
689 static void OPL3_ChannelSetupAlg(opl3_channel *channel);
690 
691 static void OPL3_ChannelUpdateRhythm(opl3_chip *chip, uint8_t data)
692 {
693  opl3_channel *channel6;
694  opl3_channel *channel7;
695  opl3_channel *channel8;
696  uint8_t chnum;
697 
698  chip->rhy = data & 0x3f;
699  if (chip->rhy & 0x20)
700  {
701  channel6 = &chip->channel[6];
702  channel7 = &chip->channel[7];
703  channel8 = &chip->channel[8];
704  channel6->out[0] = &channel6->slots[1]->out;
705  channel6->out[1] = &channel6->slots[1]->out;
706  channel6->out[2] = &chip->zeromod;
707  channel6->out[3] = &chip->zeromod;
708  channel7->out[0] = &channel7->slots[0]->out;
709  channel7->out[1] = &channel7->slots[0]->out;
710  channel7->out[2] = &channel7->slots[1]->out;
711  channel7->out[3] = &channel7->slots[1]->out;
712  channel8->out[0] = &channel8->slots[0]->out;
713  channel8->out[1] = &channel8->slots[0]->out;
714  channel8->out[2] = &channel8->slots[1]->out;
715  channel8->out[3] = &channel8->slots[1]->out;
716  for (chnum = 6; chnum < 9; chnum++)
717  {
718  chip->channel[chnum].chtype = ch_drum;
719  }
720  OPL3_ChannelSetupAlg(channel6);
721  OPL3_ChannelSetupAlg(channel7);
722  OPL3_ChannelSetupAlg(channel8);
723  //hh
724  if (chip->rhy & 0x01)
725  {
726  OPL3_EnvelopeKeyOn(channel7->slots[0], egk_drum);
727  }
728  else
729  {
730  OPL3_EnvelopeKeyOff(channel7->slots[0], egk_drum);
731  }
732  //tc
733  if (chip->rhy & 0x02)
734  {
735  OPL3_EnvelopeKeyOn(channel8->slots[1], egk_drum);
736  }
737  else
738  {
739  OPL3_EnvelopeKeyOff(channel8->slots[1], egk_drum);
740  }
741  //tom
742  if (chip->rhy & 0x04)
743  {
744  OPL3_EnvelopeKeyOn(channel8->slots[0], egk_drum);
745  }
746  else
747  {
748  OPL3_EnvelopeKeyOff(channel8->slots[0], egk_drum);
749  }
750  //sd
751  if (chip->rhy & 0x08)
752  {
753  OPL3_EnvelopeKeyOn(channel7->slots[1], egk_drum);
754  }
755  else
756  {
757  OPL3_EnvelopeKeyOff(channel7->slots[1], egk_drum);
758  }
759  //bd
760  if (chip->rhy & 0x10)
761  {
762  OPL3_EnvelopeKeyOn(channel6->slots[0], egk_drum);
763  OPL3_EnvelopeKeyOn(channel6->slots[1], egk_drum);
764  }
765  else
766  {
767  OPL3_EnvelopeKeyOff(channel6->slots[0], egk_drum);
768  OPL3_EnvelopeKeyOff(channel6->slots[1], egk_drum);
769  }
770  }
771  else
772  {
773  for (chnum = 6; chnum < 9; chnum++)
774  {
775  chip->channel[chnum].chtype = ch_2op;
776  OPL3_ChannelSetupAlg(&chip->channel[chnum]);
777  OPL3_EnvelopeKeyOff(chip->channel[chnum].slots[0], egk_drum);
778  OPL3_EnvelopeKeyOff(chip->channel[chnum].slots[1], egk_drum);
779  }
780  }
781 }
782 
783 static void OPL3_ChannelWriteA0(opl3_channel *channel, uint8_t data)
784 {
785  if (channel->chip->newm && channel->chtype == ch_4op2)
786  {
787  return;
788  }
789  channel->f_num = (channel->f_num & 0x300) | data;
790  channel->ksv = (channel->block << 1)
791  | ((channel->f_num >> (0x09 - channel->chip->nts)) & 0x01);
792  OPL3_EnvelopeUpdateKSL(channel->slots[0]);
793  OPL3_EnvelopeUpdateKSL(channel->slots[1]);
794  if (channel->chip->newm && channel->chtype == ch_4op)
795  {
796  channel->pair->f_num = channel->f_num;
797  channel->pair->ksv = channel->ksv;
798  OPL3_EnvelopeUpdateKSL(channel->pair->slots[0]);
799  OPL3_EnvelopeUpdateKSL(channel->pair->slots[1]);
800  }
801 }
802 
803 static void OPL3_ChannelWriteB0(opl3_channel *channel, uint8_t data)
804 {
805  if (channel->chip->newm && channel->chtype == ch_4op2)
806  {
807  return;
808  }
809  channel->f_num = (channel->f_num & 0xff) | ((data & 0x03) << 8);
810  channel->block = (data >> 2) & 0x07;
811  channel->ksv = (channel->block << 1)
812  | ((channel->f_num >> (0x09 - channel->chip->nts)) & 0x01);
813  OPL3_EnvelopeUpdateKSL(channel->slots[0]);
814  OPL3_EnvelopeUpdateKSL(channel->slots[1]);
815  if (channel->chip->newm && channel->chtype == ch_4op)
816  {
817  channel->pair->f_num = channel->f_num;
818  channel->pair->block = channel->block;
819  channel->pair->ksv = channel->ksv;
820  OPL3_EnvelopeUpdateKSL(channel->pair->slots[0]);
821  OPL3_EnvelopeUpdateKSL(channel->pair->slots[1]);
822  }
823 }
824 
825 static void OPL3_ChannelSetupAlg(opl3_channel *channel)
826 {
827  if (channel->chtype == ch_drum)
828  {
829  if (channel->ch_num == 7 || channel->ch_num == 8)
830  {
831  channel->slots[0]->mod = &channel->chip->zeromod;
832  channel->slots[1]->mod = &channel->chip->zeromod;
833  return;
834  }
835  switch (channel->alg & 0x01)
836  {
837  case 0x00:
838  channel->slots[0]->mod = &channel->slots[0]->fbmod;
839  channel->slots[1]->mod = &channel->slots[0]->out;
840  break;
841  case 0x01:
842  channel->slots[0]->mod = &channel->slots[0]->fbmod;
843  channel->slots[1]->mod = &channel->chip->zeromod;
844  break;
845  }
846  return;
847  }
848  if (channel->alg & 0x08)
849  {
850  return;
851  }
852  if (channel->alg & 0x04)
853  {
854  channel->pair->out[0] = &channel->chip->zeromod;
855  channel->pair->out[1] = &channel->chip->zeromod;
856  channel->pair->out[2] = &channel->chip->zeromod;
857  channel->pair->out[3] = &channel->chip->zeromod;
858  switch (channel->alg & 0x03)
859  {
860  case 0x00:
861  channel->pair->slots[0]->mod = &channel->pair->slots[0]->fbmod;
862  channel->pair->slots[1]->mod = &channel->pair->slots[0]->out;
863  channel->slots[0]->mod = &channel->pair->slots[1]->out;
864  channel->slots[1]->mod = &channel->slots[0]->out;
865  channel->out[0] = &channel->slots[1]->out;
866  channel->out[1] = &channel->chip->zeromod;
867  channel->out[2] = &channel->chip->zeromod;
868  channel->out[3] = &channel->chip->zeromod;
869  break;
870  case 0x01:
871  channel->pair->slots[0]->mod = &channel->pair->slots[0]->fbmod;
872  channel->pair->slots[1]->mod = &channel->pair->slots[0]->out;
873  channel->slots[0]->mod = &channel->chip->zeromod;
874  channel->slots[1]->mod = &channel->slots[0]->out;
875  channel->out[0] = &channel->pair->slots[1]->out;
876  channel->out[1] = &channel->slots[1]->out;
877  channel->out[2] = &channel->chip->zeromod;
878  channel->out[3] = &channel->chip->zeromod;
879  break;
880  case 0x02:
881  channel->pair->slots[0]->mod = &channel->pair->slots[0]->fbmod;
882  channel->pair->slots[1]->mod = &channel->chip->zeromod;
883  channel->slots[0]->mod = &channel->pair->slots[1]->out;
884  channel->slots[1]->mod = &channel->slots[0]->out;
885  channel->out[0] = &channel->pair->slots[0]->out;
886  channel->out[1] = &channel->slots[1]->out;
887  channel->out[2] = &channel->chip->zeromod;
888  channel->out[3] = &channel->chip->zeromod;
889  break;
890  case 0x03:
891  channel->pair->slots[0]->mod = &channel->pair->slots[0]->fbmod;
892  channel->pair->slots[1]->mod = &channel->chip->zeromod;
893  channel->slots[0]->mod = &channel->pair->slots[1]->out;
894  channel->slots[1]->mod = &channel->chip->zeromod;
895  channel->out[0] = &channel->pair->slots[0]->out;
896  channel->out[1] = &channel->slots[0]->out;
897  channel->out[2] = &channel->slots[1]->out;
898  channel->out[3] = &channel->chip->zeromod;
899  break;
900  }
901  }
902  else
903  {
904  switch (channel->alg & 0x01)
905  {
906  case 0x00:
907  channel->slots[0]->mod = &channel->slots[0]->fbmod;
908  channel->slots[1]->mod = &channel->slots[0]->out;
909  channel->out[0] = &channel->slots[1]->out;
910  channel->out[1] = &channel->chip->zeromod;
911  channel->out[2] = &channel->chip->zeromod;
912  channel->out[3] = &channel->chip->zeromod;
913  break;
914  case 0x01:
915  channel->slots[0]->mod = &channel->slots[0]->fbmod;
916  channel->slots[1]->mod = &channel->chip->zeromod;
917  channel->out[0] = &channel->slots[0]->out;
918  channel->out[1] = &channel->slots[1]->out;
919  channel->out[2] = &channel->chip->zeromod;
920  channel->out[3] = &channel->chip->zeromod;
921  break;
922  }
923  }
924 }
925 
926 static void OPL3_ChannelWriteC0(opl3_channel *channel, uint8_t data)
927 {
928  channel->fb = (data & 0x0e) >> 1;
929  channel->con = data & 0x01;
930  channel->alg = channel->con;
931  if (channel->chip->newm)
932  {
933  if (channel->chtype == ch_4op)
934  {
935  channel->pair->alg = 0x04 | (channel->con << 1) | (channel->pair->con);
936  channel->alg = 0x08;
937  OPL3_ChannelSetupAlg(channel->pair);
938  }
939  else if (channel->chtype == ch_4op2)
940  {
941  channel->alg = 0x04 | (channel->pair->con << 1) | (channel->con);
942  channel->pair->alg = 0x08;
943  OPL3_ChannelSetupAlg(channel);
944  }
945  else
946  {
947  OPL3_ChannelSetupAlg(channel);
948  }
949  }
950  else
951  {
952  OPL3_ChannelSetupAlg(channel);
953  }
954  if (channel->chip->newm)
955  {
956  channel->cha = ((data >> 4) & 0x01) ? ~0 : 0;
957  channel->chb = ((data >> 5) & 0x01) ? ~0 : 0;
958  }
959  else
960  {
961  channel->cha = channel->chb = (uint16_t)~0;
962  }
963 }
964 
965 static void OPL3_ChannelKeyOn(opl3_channel *channel)
966 {
967  if (channel->chip->newm)
968  {
969  if (channel->chtype == ch_4op)
970  {
971  OPL3_EnvelopeKeyOn(channel->slots[0], egk_norm);
972  OPL3_EnvelopeKeyOn(channel->slots[1], egk_norm);
973  OPL3_EnvelopeKeyOn(channel->pair->slots[0], egk_norm);
974  OPL3_EnvelopeKeyOn(channel->pair->slots[1], egk_norm);
975  }
976  else if (channel->chtype == ch_2op || channel->chtype == ch_drum)
977  {
978  OPL3_EnvelopeKeyOn(channel->slots[0], egk_norm);
979  OPL3_EnvelopeKeyOn(channel->slots[1], egk_norm);
980  }
981  }
982  else
983  {
984  OPL3_EnvelopeKeyOn(channel->slots[0], egk_norm);
985  OPL3_EnvelopeKeyOn(channel->slots[1], egk_norm);
986  }
987 }
988 
989 static void OPL3_ChannelKeyOff(opl3_channel *channel)
990 {
991  if (channel->chip->newm)
992  {
993  if (channel->chtype == ch_4op)
994  {
995  OPL3_EnvelopeKeyOff(channel->slots[0], egk_norm);
996  OPL3_EnvelopeKeyOff(channel->slots[1], egk_norm);
997  OPL3_EnvelopeKeyOff(channel->pair->slots[0], egk_norm);
998  OPL3_EnvelopeKeyOff(channel->pair->slots[1], egk_norm);
999  }
1000  else if (channel->chtype == ch_2op || channel->chtype == ch_drum)
1001  {
1002  OPL3_EnvelopeKeyOff(channel->slots[0], egk_norm);
1003  OPL3_EnvelopeKeyOff(channel->slots[1], egk_norm);
1004  }
1005  }
1006  else
1007  {
1008  OPL3_EnvelopeKeyOff(channel->slots[0], egk_norm);
1009  OPL3_EnvelopeKeyOff(channel->slots[1], egk_norm);
1010  }
1011 }
1012 
1013 static void OPL3_ChannelSet4Op(opl3_chip *chip, uint8_t data)
1014 {
1015  uint8_t bit;
1016  uint8_t chnum;
1017  for (bit = 0; bit < 6; bit++)
1018  {
1019  chnum = bit;
1020  if (bit >= 3)
1021  {
1022  chnum += 9 - 3;
1023  }
1024  if ((data >> bit) & 0x01)
1025  {
1026  chip->channel[chnum].chtype = ch_4op;
1027  chip->channel[chnum + 3].chtype = ch_4op2;
1028  }
1029  else
1030  {
1031  chip->channel[chnum].chtype = ch_2op;
1032  chip->channel[chnum + 3].chtype = ch_2op;
1033  }
1034  }
1035 }
1036 
1037 static int16_t OPL3_ClipSample(int32_t sample)
1038 {
1039  if (sample > 32767)
1040  {
1041  sample = 32767;
1042  }
1043  else if (sample < -32768)
1044  {
1045  sample = -32768;
1046  }
1047  return (int16_t)sample;
1048 }
1049 
1050 void OPL3_Generate(opl3_chip *chip, int16_t *buf)
1051 {
1052  uint8_t ii;
1053  uint8_t jj;
1054  int16_t accm;
1055  uint8_t shift = 0;
1056 
1057  buf[1] = OPL3_ClipSample(chip->mixbuff[1]);
1058 
1059  for (ii = 0; ii < 15; ii++)
1060  {
1061  OPL3_SlotCalcFB(&chip->slot[ii]);
1062  OPL3_EnvelopeCalc(&chip->slot[ii]);
1063  OPL3_PhaseGenerate(&chip->slot[ii]);
1064  OPL3_SlotGenerate(&chip->slot[ii]);
1065  }
1066 
1067  chip->mixbuff[0] = 0;
1068  for (ii = 0; ii < 18; ii++)
1069  {
1070  accm = 0;
1071  for (jj = 0; jj < 4; jj++)
1072  {
1073  accm += *chip->channel[ii].out[jj];
1074  }
1075  chip->mixbuff[0] += (int16_t)(accm & chip->channel[ii].cha);
1076  }
1077 
1078  for (ii = 15; ii < 18; ii++)
1079  {
1080  OPL3_SlotCalcFB(&chip->slot[ii]);
1081  OPL3_EnvelopeCalc(&chip->slot[ii]);
1082  OPL3_PhaseGenerate(&chip->slot[ii]);
1083  OPL3_SlotGenerate(&chip->slot[ii]);
1084  }
1085 
1086  buf[0] = OPL3_ClipSample(chip->mixbuff[0]);
1087 
1088  for (ii = 18; ii < 33; ii++)
1089  {
1090  OPL3_SlotCalcFB(&chip->slot[ii]);
1091  OPL3_EnvelopeCalc(&chip->slot[ii]);
1092  OPL3_PhaseGenerate(&chip->slot[ii]);
1093  OPL3_SlotGenerate(&chip->slot[ii]);
1094  }
1095 
1096  chip->mixbuff[1] = 0;
1097  for (ii = 0; ii < 18; ii++)
1098  {
1099  accm = 0;
1100  for (jj = 0; jj < 4; jj++)
1101  {
1102  accm += *chip->channel[ii].out[jj];
1103  }
1104  chip->mixbuff[1] += (int16_t)(accm & chip->channel[ii].chb);
1105  }
1106 
1107  for (ii = 33; ii < 36; ii++)
1108  {
1109  OPL3_SlotCalcFB(&chip->slot[ii]);
1110  OPL3_EnvelopeCalc(&chip->slot[ii]);
1111  OPL3_PhaseGenerate(&chip->slot[ii]);
1112  OPL3_SlotGenerate(&chip->slot[ii]);
1113  }
1114 
1115  if ((chip->timer & 0x3f) == 0x3f)
1116  {
1117  chip->tremolopos = (chip->tremolopos + 1) % 210;
1118  }
1119  if (chip->tremolopos < 105)
1120  {
1121  chip->tremolo = chip->tremolopos >> chip->tremoloshift;
1122  }
1123  else
1124  {
1125  chip->tremolo = (210 - chip->tremolopos) >> chip->tremoloshift;
1126  }
1127 
1128  if ((chip->timer & 0x3ff) == 0x3ff)
1129  {
1130  chip->vibpos = (chip->vibpos + 1) & 7;
1131  }
1132 
1133  chip->timer++;
1134 
1135  chip->eg_add = 0;
1136  if (chip->eg_timer)
1137  {
1138  while (shift < 36 && ((chip->eg_timer >> shift) & 1) == 0)
1139  {
1140  shift++;
1141  }
1142  if (shift > 12)
1143  {
1144  chip->eg_add = 0;
1145  }
1146  else
1147  {
1148  chip->eg_add = shift + 1;
1149  }
1150  }
1151 
1152  if (chip->eg_timerrem || chip->eg_state)
1153  {
1154  if (chip->eg_timer == 0xfffffffff)
1155  {
1156  chip->eg_timer = 0;
1157  chip->eg_timerrem = 1;
1158  }
1159  else
1160  {
1161  chip->eg_timer++;
1162  chip->eg_timerrem = 0;
1163  }
1164  }
1165 
1166  chip->eg_state ^= 1;
1167 
1168  while (chip->writebuf[chip->writebuf_cur].time <= chip->writebuf_samplecnt)
1169  {
1170  if (!(chip->writebuf[chip->writebuf_cur].reg & 0x200))
1171  {
1172  break;
1173  }
1174  chip->writebuf[chip->writebuf_cur].reg &= 0x1ff;
1175  OPL3_WriteReg(chip, chip->writebuf[chip->writebuf_cur].reg,
1176  chip->writebuf[chip->writebuf_cur].data);
1177  chip->writebuf_cur = (chip->writebuf_cur + 1) % OPL_WRITEBUF_SIZE;
1178  }
1179  chip->writebuf_samplecnt++;
1180 }
1181 
1182 void OPL3_GenerateResampled(opl3_chip *chip, int16_t *buf1, int16_t *buf2)
1183 {
1184  while (chip->samplecnt >= chip->rateratio)
1185  {
1186  chip->oldsamples[0] = chip->samples[0];
1187  chip->oldsamples[1] = chip->samples[1];
1188  OPL3_Generate(chip, chip->samples);
1189  chip->samplecnt -= chip->rateratio;
1190  }
1191  buf1[0] = (int16_t)((chip->oldsamples[0] * (chip->rateratio - chip->samplecnt)
1192  + chip->samples[0] * chip->samplecnt) / chip->rateratio);
1193  buf2[0] = (int16_t)((chip->oldsamples[1] * (chip->rateratio - chip->samplecnt)
1194  + chip->samples[1] * chip->samplecnt) / chip->rateratio);
1195  chip->samplecnt += 1 << RSM_FRAC;
1196 }
1197 
1198 void OPL3_Reset(opl3_chip *chip, uint32_t samplerate)
1199 {
1200  uint8_t slotnum;
1201  uint8_t channum;
1202 
1203  memset(chip, 0, sizeof(opl3_chip));
1204  for (slotnum = 0; slotnum < 36; slotnum++)
1205  {
1206  chip->slot[slotnum].chip = chip;
1207  chip->slot[slotnum].mod = &chip->zeromod;
1208  chip->slot[slotnum].eg_rout = 0x1ff;
1209  chip->slot[slotnum].eg_out = 0x1ff;
1210  chip->slot[slotnum].eg_gen = envelope_gen_num_release;
1211  chip->slot[slotnum].trem = (uint8_t*)&chip->zeromod;
1212  chip->slot[slotnum].slot_num = slotnum;
1213  }
1214  for (channum = 0; channum < 18; channum++)
1215  {
1216  chip->channel[channum].slots[0] = &chip->slot[ch_slot[channum]];
1217  chip->channel[channum].slots[1] = &chip->slot[ch_slot[channum] + 3];
1218  chip->slot[ch_slot[channum]].channel = &chip->channel[channum];
1219  chip->slot[ch_slot[channum] + 3].channel = &chip->channel[channum];
1220  if ((channum % 9) < 3)
1221  {
1222  chip->channel[channum].pair = &chip->channel[channum + 3];
1223  }
1224  else if ((channum % 9) < 6)
1225  {
1226  chip->channel[channum].pair = &chip->channel[channum - 3];
1227  }
1228  chip->channel[channum].chip = chip;
1229  chip->channel[channum].out[0] = &chip->zeromod;
1230  chip->channel[channum].out[1] = &chip->zeromod;
1231  chip->channel[channum].out[2] = &chip->zeromod;
1232  chip->channel[channum].out[3] = &chip->zeromod;
1233  chip->channel[channum].chtype = ch_2op;
1234  chip->channel[channum].cha = 0xffff;
1235  chip->channel[channum].chb = 0xffff;
1236  chip->channel[channum].ch_num = channum;
1237  OPL3_ChannelSetupAlg(&chip->channel[channum]);
1238  }
1239  chip->noise = 1;
1240  chip->rateratio = (samplerate << RSM_FRAC) / 49716;
1241  chip->tremoloshift = 4;
1242  chip->vibshift = 1;
1243 }
1244 
1245 void OPL3_WriteReg(opl3_chip *chip, uint16_t reg, uint8_t v)
1246 {
1247  uint8_t high = (reg >> 8) & 0x01;
1248  uint8_t regm = reg & 0xff;
1249  switch (regm & 0xf0)
1250  {
1251  case 0x00:
1252  if (high)
1253  {
1254  switch (regm & 0x0f)
1255  {
1256  case 0x04:
1257  OPL3_ChannelSet4Op(chip, v);
1258  break;
1259  case 0x05:
1260  chip->newm = v & 0x01;
1261  break;
1262  }
1263  }
1264  else
1265  {
1266  switch (regm & 0x0f)
1267  {
1268  case 0x08:
1269  chip->nts = (v >> 6) & 0x01;
1270  break;
1271  }
1272  }
1273  break;
1274  case 0x20:
1275  case 0x30:
1276  if (ad_slot[regm & 0x1f] >= 0)
1277  {
1278  OPL3_SlotWrite20(&chip->slot[18 * high + ad_slot[regm & 0x1f]], v);
1279  }
1280  break;
1281  case 0x40:
1282  case 0x50:
1283  if (ad_slot[regm & 0x1f] >= 0)
1284  {
1285  OPL3_SlotWrite40(&chip->slot[18 * high + ad_slot[regm & 0x1f]], v);
1286  }
1287  break;
1288  case 0x60:
1289  case 0x70:
1290  if (ad_slot[regm & 0x1f] >= 0)
1291  {
1292  OPL3_SlotWrite60(&chip->slot[18 * high + ad_slot[regm & 0x1f]], v);
1293  }
1294  break;
1295  case 0x80:
1296  case 0x90:
1297  if (ad_slot[regm & 0x1f] >= 0)
1298  {
1299  OPL3_SlotWrite80(&chip->slot[18 * high + ad_slot[regm & 0x1f]], v);
1300  }
1301  break;
1302  case 0xe0:
1303  case 0xf0:
1304  if (ad_slot[regm & 0x1f] >= 0)
1305  {
1306  OPL3_SlotWriteE0(&chip->slot[18 * high + ad_slot[regm & 0x1f]], v);
1307  }
1308  break;
1309  case 0xa0:
1310  if ((regm & 0x0f) < 9)
1311  {
1312  OPL3_ChannelWriteA0(&chip->channel[9 * high + (regm & 0x0f)], v);
1313  }
1314  break;
1315  case 0xb0:
1316  if (regm == 0xbd && !high)
1317  {
1318  chip->tremoloshift = (((v >> 7) ^ 1) << 1) + 2;
1319  chip->vibshift = ((v >> 6) & 0x01) ^ 1;
1320  OPL3_ChannelUpdateRhythm(chip, v);
1321  }
1322  else if ((regm & 0x0f) < 9)
1323  {
1324  OPL3_ChannelWriteB0(&chip->channel[9 * high + (regm & 0x0f)], v);
1325  if (v & 0x20)
1326  {
1327  OPL3_ChannelKeyOn(&chip->channel[9 * high + (regm & 0x0f)]);
1328  }
1329  else
1330  {
1331  OPL3_ChannelKeyOff(&chip->channel[9 * high + (regm & 0x0f)]);
1332  }
1333  }
1334  break;
1335  case 0xc0:
1336  if ((regm & 0x0f) < 9)
1337  {
1338  OPL3_ChannelWriteC0(&chip->channel[9 * high + (regm & 0x0f)], v);
1339  }
1340  break;
1341  }
1342 }
1343 
1344 void OPL3_WriteRegBuffered(opl3_chip *chip, uint16_t reg, uint8_t v)
1345 {
1346  uint64_t time1, time2;
1347 
1348  if (chip->writebuf[chip->writebuf_last].reg & 0x200)
1349  {
1350  OPL3_WriteReg(chip, chip->writebuf[chip->writebuf_last].reg & 0x1ff,
1351  chip->writebuf[chip->writebuf_last].data);
1352 
1353  chip->writebuf_cur = (chip->writebuf_last + 1) % OPL_WRITEBUF_SIZE;
1354  chip->writebuf_samplecnt = chip->writebuf[chip->writebuf_last].time;
1355  }
1356 
1357  chip->writebuf[chip->writebuf_last].reg = reg | 0x200;
1358  chip->writebuf[chip->writebuf_last].data = v;
1359  time1 = chip->writebuf_lasttime + OPL_WRITEBUF_DELAY;
1360  time2 = chip->writebuf_samplecnt;
1361 
1362  if (time1 < time2)
1363  {
1364  time1 = time2;
1365  }
1366 
1367  chip->writebuf[chip->writebuf_last].time = time1;
1368  chip->writebuf_lasttime = time1;
1369  chip->writebuf_last = (chip->writebuf_last + 1) % OPL_WRITEBUF_SIZE;
1370 }
1371 
1372 void OPL3_GenerateStream(opl3_chip *chip, int16_t *sndptr1, int16_t *sndptr2, uint32_t numsamples, const uint32_t increment1, const uint32_t increment2 )
1373 {
1374  /* Comment from LGB:
1375  Originally Nuked-OPL3 generated interleaved stereo stream (see the "original code was" part above).
1376  I modified this to have two buffer pointers passed, and also too increment values.
1377  This way, the interleaved scheme can be still 'simulated' but also, separate buffers can be used,
1378  what is my intent for Xemu.
1379  */
1380  while (numsamples--) {
1381  OPL3_GenerateResampled(chip, sndptr1, sndptr2);
1382  sndptr1 += increment1;
1383  sndptr2 += increment2;
1384  }
1385  /* // Original code was:
1386  uint32_t i;
1387 
1388  for(i = 0; i < numsamples; i++)
1389  {
1390  OPL3_GenerateResampled(chip, sndptr);
1391  sndptr += 2;
1392  }
1393  */
1394 }
_opl3_channel::pair
opl3_channel * pair
Definition: opl3.h:79
OPL_WRITEBUF_SIZE
#define OPL_WRITEBUF_SIZE
Definition: opl3.h:38
envelope_sinfunc
int16_t(* envelope_sinfunc)(uint16_t phase, uint16_t envelope)
Definition: opl3.c:185
_opl3_chip::writebuf_last
uint32_t writebuf_last
Definition: opl3.h:132
ch_drum
@ ch_drum
Definition: opl3.c:46
_opl3_slot::eg_out
uint16_t eg_out
Definition: opl3.h:53
exprom
Uint8 exprom[0x8000]
Definition: primo.c:45
_opl3_chip::mixbuff
int32_t mixbuff[2]
Definition: opl3.h:117
_opl3_slot::key
uint8_t key
Definition: opl3.h:70
_opl3_chip::eg_state
uint8_t eg_state
Definition: opl3.h:105
_opl3_chip::rm_hh_bit7
uint8_t rm_hh_bit7
Definition: opl3.h:120
_opl3_slot::pg_phase
uint32_t pg_phase
Definition: opl3.h:72
_opl3_slot::reg_wf
uint8_t reg_wf
Definition: opl3.h:69
_opl3_channel::cha
uint16_t cha
Definition: opl3.h:89
_opl3_slot::reg_dr
uint8_t reg_dr
Definition: opl3.h:66
OPL3_GenerateStream
void OPL3_GenerateStream(opl3_chip *chip, int16_t *sndptr1, int16_t *sndptr2, uint32_t numsamples, const uint32_t increment1, const uint32_t increment2)
Definition: opl3.c:1372
_opl3_chip::rhy
uint8_t rhy
Definition: opl3.h:109
_opl3_chip::samples
int16_t samples[2]
Definition: opl3.h:128
_opl3_slot::reg_tl
uint8_t reg_tl
Definition: opl3.h:64
_opl3_slot::reg_ksr
uint8_t reg_ksr
Definition: opl3.h:61
_opl3_chip::writebuf_samplecnt
uint64_t writebuf_samplecnt
Definition: opl3.h:130
_opl3_chip::rateratio
int32_t rateratio
Definition: opl3.h:125
_opl3_slot::reg_sl
uint8_t reg_sl
Definition: opl3.h:67
_opl3_chip::vibpos
uint8_t vibpos
Definition: opl3.h:110
_opl3_slot::reg_ksl
uint8_t reg_ksl
Definition: opl3.h:63
_opl3_channel::f_num
uint16_t f_num
Definition: opl3.h:83
_opl3_chip::nts
uint8_t nts
Definition: opl3.h:108
_opl3_slot::fbmod
int16_t fbmod
Definition: opl3.h:49
_opl3_writebuf::data
uint8_t data
Definition: opl3.h:96
_opl3_chip::samplecnt
int32_t samplecnt
Definition: opl3.h:126
envelope_gen_num
envelope_gen_num
Definition: opl3.c:345
_opl3_slot::out
int16_t out
Definition: opl3.h:48
egk_drum
@ egk_drum
Definition: opl3.c:53
_opl3_slot::reg_ar
uint8_t reg_ar
Definition: opl3.h:65
m65-memcontent-generator.data
data
Definition: m65-memcontent-generator.py:119
_opl3_chip::tremoloshift
uint8_t tremoloshift
Definition: opl3.h:114
_opl3_channel::alg
uint8_t alg
Definition: opl3.h:87
_opl3_chip::noise
uint32_t noise
Definition: opl3.h:115
_opl3_chip::eg_timer
uint64_t eg_timer
Definition: opl3.h:103
_opl3_chip::newm
uint8_t newm
Definition: opl3.h:107
_opl3_channel::slots
opl3_slot * slots[2]
Definition: opl3.h:78
RSM_FRAC
#define RSM_FRAC
Definition: opl3.c:38
_opl3_channel::ksv
uint8_t ksv
Definition: opl3.h:88
_opl3_chip::slot
opl3_slot slot[36]
Definition: opl3.h:101
_opl3_slot::pg_phase_out
uint16_t pg_phase_out
Definition: opl3.h:73
_opl3_chip::eg_add
uint8_t eg_add
Definition: opl3.h:106
_opl3_chip::rm_hh_bit8
uint8_t rm_hh_bit8
Definition: opl3.h:121
_opl3_chip::vibshift
uint8_t vibshift
Definition: opl3.h:111
opl3.h
_opl3_chip::writebuf_cur
uint32_t writebuf_cur
Definition: opl3.h:131
_opl3_chip::tremolo
uint8_t tremolo
Definition: opl3.h:112
_opl3_slot::reg_mult
uint8_t reg_mult
Definition: opl3.h:62
_opl3_channel::chip
opl3_chip * chip
Definition: opl3.h:80
_opl3_channel::out
int16_t * out[4]
Definition: opl3.h:81
_opl3_slot::slot_num
uint8_t slot_num
Definition: opl3.h:74
ch_2op
@ ch_2op
Definition: opl3.c:43
_opl3_channel::con
uint8_t con
Definition: opl3.h:86
_opl3_chip::rm_tc_bit3
uint8_t rm_tc_bit3
Definition: opl3.h:122
_opl3_chip::channel
opl3_channel channel[18]
Definition: opl3.h:100
_opl3_channel::chtype
uint8_t chtype
Definition: opl3.h:82
_opl3_chip::rm_hh_bit3
uint8_t rm_hh_bit3
Definition: opl3.h:119
_opl3_slot::reg_type
uint8_t reg_type
Definition: opl3.h:60
_opl3_writebuf::time
uint64_t time
Definition: opl3.h:94
_opl3_slot
Definition: opl3.h:45
OPL_WRITEBUF_DELAY
#define OPL_WRITEBUF_DELAY
Definition: opl3.h:39
_opl3_slot::reg_rr
uint8_t reg_rr
Definition: opl3.h:68
_opl3_chip::tremolopos
uint8_t tremolopos
Definition: opl3.h:113
_opl3_slot::prout
int16_t prout
Definition: opl3.h:51
_opl3_channel::block
uint8_t block
Definition: opl3.h:84
_opl3_channel::fb
uint8_t fb
Definition: opl3.h:85
_opl3_slot::eg_gen
uint8_t eg_gen
Definition: opl3.h:55
phase
int phase
Definition: commodore_lcd.c:73
OPL3_Reset
void OPL3_Reset(opl3_chip *chip, uint32_t samplerate)
Definition: opl3.c:1198
_opl3_slot::mod
int16_t * mod
Definition: opl3.h:50
_opl3_slot::reg_vib
uint8_t reg_vib
Definition: opl3.h:59
_opl3_channel
Definition: opl3.h:77
_opl3_slot::trem
uint8_t * trem
Definition: opl3.h:58
envelope_gen_num_attack
@ envelope_gen_num_attack
Definition: opl3.c:347
OPL3_Generate
void OPL3_Generate(opl3_chip *chip, int16_t *buf)
Definition: opl3.c:1050
envelope_gen_num_decay
@ envelope_gen_num_decay
Definition: opl3.c:348
envelope_gen_num_release
@ envelope_gen_num_release
Definition: opl3.c:350
_opl3_slot::eg_rout
uint16_t eg_rout
Definition: opl3.h:52
_opl3_chip
Definition: opl3.h:99
_opl3_slot::channel
opl3_channel * channel
Definition: opl3.h:46
ch_4op2
@ ch_4op2
Definition: opl3.c:45
egk_norm
@ egk_norm
Definition: opl3.c:52
OPL3_WriteReg
void OPL3_WriteReg(opl3_chip *chip, uint16_t reg, uint8_t v)
Definition: opl3.c:1245
OPL3_WriteRegBuffered
void OPL3_WriteRegBuffered(opl3_chip *chip, uint16_t reg, uint8_t v)
Definition: opl3.c:1344
_opl3_slot::chip
opl3_chip * chip
Definition: opl3.h:47
ch_4op
@ ch_4op
Definition: opl3.c:44
_opl3_channel::ch_num
uint8_t ch_num
Definition: opl3.h:90
_opl3_chip::rm_hh_bit2
uint8_t rm_hh_bit2
Definition: opl3.h:118
_opl3_channel::chb
uint16_t chb
Definition: opl3.h:89
_opl3_chip::writebuf_lasttime
uint64_t writebuf_lasttime
Definition: opl3.h:133
OPL3_GenerateResampled
void OPL3_GenerateResampled(opl3_chip *chip, int16_t *buf1, int16_t *buf2)
Definition: opl3.c:1182
_opl3_chip::oldsamples
int16_t oldsamples[2]
Definition: opl3.h:127
_opl3_slot::eg_ksl
uint8_t eg_ksl
Definition: opl3.h:57
_opl3_writebuf::reg
uint16_t reg
Definition: opl3.h:95
envelope_genfunc
void(* envelope_genfunc)(opl3_slot *slott)
Definition: opl3.c:186
_opl3_slot::pg_reset
uint32_t pg_reset
Definition: opl3.h:71
_opl3_chip::timer
uint16_t timer
Definition: opl3.h:102
_opl3_chip::eg_timerrem
uint8_t eg_timerrem
Definition: opl3.h:104
_opl3_chip::zeromod
int16_t zeromod
Definition: opl3.h:116
_opl3_chip::rm_tc_bit5
uint8_t rm_tc_bit5
Definition: opl3.h:123
buf
Uint8 buf[512]
Definition: fat32.c:155
_opl3_chip::writebuf
opl3_writebuf writebuf[OPL_WRITEBUF_SIZE]
Definition: opl3.h:134
envelope_gen_num_sustain
@ envelope_gen_num_sustain
Definition: opl3.c:349